FIG. 5 shows the circuit configuration of a load resonance power conversion apparatus (ac/dc conversion apparatus) connected with a resonant load. In FIG. 5, an ac/dc conversion apparatus or converter 10 is provided with a single-phase inverter having an input side connected with a dc voltage source 11, and an output side connected with a resonant load 12 such as an inductive heating circuit. The conversion apparatus 10 outputs a rectangular or square voltage at a resonance frequency to the resonant load 12 by on/off control of each switching device of the single-phase inverter.
In the case of the resonant load 12 being an induction heating circuit, this ac/dc conversion apparatus 10 is constructed as an induction heating load resonance ac/dc conversion apparatus (induction heating resonance type inverter).
This induction heating load resonance ac/dc conversion apparatus leads an alternating current produced by the on/off control of each switching device in the single-phase inverter, through a LC resonance circuit of coil and capacitor, applies the thus-generated alternating magnetic field to an object to be heated (electric conductor) thereby to produce eddy currents, and heats the object from the inside with the Joule heat generated in the object by the eddy currents.
In the induction heating circuit connected, as the resonant load, with the output side of the load resonance power conversion apparatus (the ac/dc conversion apparatus 10 of FIG. 5, for example), the depth of electric current penetration decreases as the frequency becomes higher, as is known from before.
In an electric resistance welded pipe joining (to produce a pipe or tube by joining a seam by electric resistance welding), to perform surface quenching, the load resonance ac/dc conversion apparatus is required to produce a voltage of a high frequency.
On the other hand, the switching devices in the load resonance ac/dc conversion apparatus used for the induction heating are unable to cope with voltage frequencies higher than the upper limit of drive frequency of the switching devices.
To solve this problem, a resonant load inverter system is proposed in a patent document 1, for example. As disclosed in FIG. 3 and described in this patent document, the parallel connection of N sections of series connected upper and lower switching devices makes it possible to drive the switching devices with 1/N cycle or period. Accordingly, for a desired resonance frequency, it is possible to decrease the drive frequency of the switching devices to a frequency inversely proportional to the number of parallel connected sections.
Moreover, a variation example of the resonant load inverter system of the patent document 1 is conceivable as shown in FIG. 6. In this variable example of FIG. 6, each arm of the single-phase inverter has an N parallel arrangement of switching devices (IGBT, for example).
The apparatus of FIG. 6 is a load resonance ac/dc conversion apparatus which can be used in the ac/dc conversion apparatus 10 of FIG. 5, for example. This apparatus includes a dc link voltage input section Vdc, a rectangular or square voltage output section Vout, and a single-phase inverter including N (three in this example) parallel connected switching devices (U11, U21, U31; V11, V21, V31; X11, X21, X31; and Y11, Y21, Y31) in each arm.
By increasing the number N of the switching devices connected in parallel in each arm as the example of FIG. 6, it is possible to decrease the switching frequency per one switching device as in the resonant load inverter system of the patent document 1.
Each of the switching devices of FIG. 6 is controlled between ON and OFF according to gate command signal generating patterns shown in FIG. 7.
The gate command signal generating patterns of FIG. 7 include a clock signal using, as trigger, ON, OFF changes of an output voltage command (Vout_ref) of the signal-phase inverter and following gate command signals which are periodical with a period or cycle period of 6 clocks or 6 clock intervals. A U11/Y11 gate command signal U11_gate/Y11_gate for the switching devices U11 and Y11 periodically outputs an ON signal for one clock and an OFF signal for five clocks. A X11/V11 gate command signal X11_gate/V11_gate for the switching devices X11 and V11 is delayed by one clock from the gate command signal U11_gate/Y11_gate but has the same on period and off period as the ON period and OFF period of the U11/Y11 gate command signal U11_gate/Y11_gate. A U21/Y21 gate command signal U21_gate/Y21_gate for the switching devices U21 and Y21 is delayed by one clock from the gate command signal X11_gate/V11_gate but has the same on period and off period as the ON period and OFF period of the gate command signal X11_gate/V11_gate. A X21/V21 gate command signal X21_gate/V21_gate for the switching devices X21 and V21 is delayed by one clock from the gate command signal U21_gate/Y21_gate but has the same on period and off period as the ON period and OFF period of the gate command signal U21_gate/Y21_gate. A U31/Y31 gate command signal U21_gate/Y21_gate for the switching devices U31 and Y31 is delayed by one clock from the gate command signal X21_gate/V21_gate but has the same on period and off period as the ON period and OFF period of the gate command signal X21_gate/V11_gate. A X31/V31 gate command signal X31_gate/V31_gate for the switching devices X31 and V31 is delayed by one clock from the gate command signal U31_gate/Y31_gate but has the same on period and off period as the ON period and OFF period of the gate command signal U31_gate/Y31_gate.
Each of the switching devices of FIG. 6 is controlled between ON and OFF by one of the thus-produced gate command signals U11_gate/Y11_gate X31_gate/V31_gate in the manner of repetition of patterns (1)˜(6) shown in FIG. 8(a) to FIG. 8(f).
FIG. 8 shows the output current when the switching devices of FIG. 6 are driven by the gate command signal generation patterns of FIG. 7.
FIGS. 8(a)˜8(f) correspond to the patterns (1)˜(6) of FIG. 7, respectively. In each figure, “ON” indicates the switching devices tuned ON by the ON signal of the gate command, and arrows indicate the path of output current Iout flowing through the ON controlled switching devices and the load.
As evident from FIGS. 7 and 8, the switching frequency (drive frequency) of the command for each switching device is decreased by (⅓) (1/N) by sequential switching operations of the patterns (1)˜(6).